1. Field of the Invention
The present invention relates to an M-ISDN (multi-integrated services digital network), and more particularly, to a frame synchronizing apparatus using a memory in which a frame synchronizing algorithm is embodied in an ASIC (application specific integrated circuit) so as to be employed in a circuit for synchronizing the frame in framing/deframing method for improving performance of ATM (asynchronous transfer mode) cell extraction in high-error wireless environment or WATM (wireless asynchronous transfer mode), and such an algorithm can be employed in a circuit for synchronizing the frame in a received data stream.
2. Description of the Related Art
In general, a frame synchronization algorithm is a portion for synchronizing the frame in a deframer block. The frame synchronization algorithm receives data, and detects synchronization signal from a frame header or sub-frame header. Then, the frame synchronization algorithm makes a payroad portion into cell units, and sends the result to a cell boundary discriminating block with a cell synchronization signal.
A conventional algorithm for detecting a frame synchronization signal based on an STM (state machine) is executed in a wire network having low error rate, and specifically, in an environment where a byte synchronization signal is arranged. A problem may arise when such an algorithm is executed in a wireless environment having a high error rate. Therefore, a synchronization algorithm for overcoming such a high error is required.
FIG. 1 illustrates a conventional frame structure which is considered as desirable when it allows stable extraction of ATM cell in an environment having a high error rate.
Referring to FIG. 1, F denotes a framing header of 2-bytes and has a value of F628 (H), S denotes a sub-frame header of 1-byte and has a value of E8 (H). L denotes a link control channel for exchanging state data between links, O denotes an order wire channel for use in voice communication, and R denotes a reserved channel.
The frame structure has 45 ATM cells, and each ATM cell consists of 53-bytes. A single sub-frame consists of 270 bytes (5+53xc3x975), thus a single frame consists of 2430 (270xc3x979) bytes.
In most cases, system synchronization can be checked by detecting periodical arrival of frame head pattern F628 and sub-frame header pattern E8 at a receiving side.
In an asynchronized state, regularity of simple header patterns may be sought for a resynchronization.
It is desirable to use smaller-sized sub-frame header and frame header so as to reduce an error which may occur at the header, and the sub-frame header and frame header are employed for a convenient and rapid synchronization.
As for the data received from outside, a deframing process is performed. FIG. 2 shows an OOF (out of frame) state and FS (frame synchronization) state, which may occur when such a deframing process is performed.
The OOF state is where two consecutive errors occur at the frame header pattern or sub-frame header pattern, and six consecutive errors occur at the cell boundary discriminating block.
To return to the frame synchronization state, it is required that the last four sub-frames have three error-zero frame headers or sub-frame headers.
As described above, only the sub-frame header and frame header are checked, thus allowing a rapid synchronization in a high-error environment.
Frame synchronization may be more easily obtained by comparing the sub-frame header and the frame header without performing an HEC (header error check) for the cell header.
In such a conventional cell-based method, cell extraction is accomplished only by an HEC. However, in the frame-based cell extraction algorithm, an HEC is performed for the sub-frame header, frame header, and cell-header.
A process of implementing frame synchronization algorithm using a conventional shift register will be explained with reference to FIG. 3.
Referring to FIG. 3, an apparatus for implementing the frame synchronization algorithm includes a shift register 11 of 812-bytes for storing three sub-frames and headers H1 to H4, a pattern comparing unit 12 for comparing four header values, two adders 13 and 14 for adding an output of the pattern comparing unit 12, a synchronization declaration unit 15 for declaring synchronization or asynchronization from an output of adders 13 and 14.
In such a configuration using a conventional shift register, the input data enters into the shift register 11 for storing three sub-frames and the four headers H1 to H4.
When the output of the shift register 11 enters into the pattern comparing unit 12, the pattern comparing unit 12 compares four header (frame header or sub-frame header) values. If the value is larger than 3, the synchronization declaration unit 15 outputs a sub-frame header synchronization signal sfrm_sync and declares frame synchronization (FS), thus generating a header enable signal.
At the FS state, a frame header synchronization signal frm_sync is output. Then, referring to the most recent headers H1 and H2, asynchronization (OOF) is declared if HEC_error value is 1.
FIG. 3 illustrates a case where the shift register 11 is used as a history buffer.
In such a conventional configuration, the deframer requires frame synchronization signal for a stable ATM cell extraction in a high-error wireless environment or WATM. In addition, the shift register is used as means for storing data of four sub-frames. However, the shift register 11 of 812-bytes may significantly increase a circuit volume, and ASIC gate to 80,000 or higher. Thus, a single frame synchronization unit may constitute an ASIC. However, the frame synchronization unit may not constitute an ASIC together with other blocks (e.g., FEC (forward error correcting) block).
Therefore, it is an object of the present invention to significantly reduce number of gates by implementing a history buffer using a memory in a frame synchronization algorithm.
To accomplish the above object of the present invention, there is provided a frame synchronizing apparatus using a memory in which three counters of which reset values differ from each other by one sub-frame unit are employed so as to designate a write address and a read address, and a bit clock is used so as to process four readings during a period of one data cycle.